The SensiML Knowledge Pack consists of the complete code required to transform raw sensor into classified insights as trained from datasets and ground truth labels you supply for your application. The resulting inference model is optimized to fit constraints as you prescribe and encompasses event detection, pre-processing, feature extraction, classification algorithms, and post-processing.
Using the SensiML Analytics Studio users can optimize their algorithm either through AutoML or through an expert user interface of plug and play building blocks using SensiML Analytics Studio Notebook and our rich library of device optimized functions.
Download SensiML Technical Overview >
Whether your needs require edge algorithm execution or edge adaptive learning models, SensiML Knowledge Packs can accommodate your application.
For applications where a defined edge algorithm meets the need, Knowledge Packs can be easily constructed and tested in the cloud and deployed to the edge device. Developers may implement any mechanism to associate or update a device with a given Knowledge Pack based on contextual information or user preference for that device. Model selection can utilize universal models or be more narrowly defined based on metadata that links to Knowledge Packs trained on specific subsets of data.
For those applications that demand true per-instance customization, this can also be achieved using adaptive edge model tuning. This more advanced feature is an available option for users to implement personalized model parameters from true on-device tuning using the SensiML API to adjust model weights and parameters locally.
| Preprocessing | Feature Extraction | Classification Methods |
|---|---|---|
|
|
|
For a complete list, see supporting documentation included with the SensiML Analytics Studio.
We have created 10 video tutorials to help you every step of the way.
Watch Videos
SensiML supports a range of hardware architectures:
Choose your desired architecture and SensiML AutoML will tailor Knowledge Pack code to provide power/performance optimization utilizing the ISA and HW accelerators available on the target system.
